RTL-ASIC Engineer

Bangalore | 5 Years


Key Responsibilities

  • Experienced In Rtl Design Using Verilog / System Verilog
  • Asic Designers With Experiences In All Aspects Of Rtl Design Flow From Specification/microarchitecture Definition To Design And Verification, Timing Analysis, Dft And Implementation
  • Integration, Rtl Signoff Tools, Upf/low Power Signoff And Cdc/rdc, Lint
  • Strong Domain Knowledge Of Clocking,system Modes. Power Management, Debug, Interconnect, Safety, Security And Other Architectures

Apply Now

    Most Popular

    | 0 Min Read

    Security Firmware Development

    | 0 Min Read

    Physical Design Engineer Lead

    | 0 Min Read

    Conformal Low Power [CLP]

    | 0 Min Read

    Senior Design Verification Engineer