RTL-ASIC Engineer

Bangalore | 5+ Years

Key Roles

• Experienced in rtl design using verilog / system Verilog
• Asic designers with experiences in all aspects of rtl design flow from specification/microarchitecture definition to design and verification, timing analysis, dft and implementation
• Integration, rtl signoff tools, upf/low power signoff and cdc/rdc, lint
• Strong domain knowledge of clocking, system modes. Power management, debug, interconnect, safety, security and other architectures