RTL-ASIC Engineer

Bangalore | 5 Years

Key Responsibilities

• Experienced In Rtl Design Using Verilog / System Verilog
• Asic Designers With Experiences In All Aspects Of Rtl Design Flow From Specification/microarchitecture Definition To Design And Verification, Timing Analysis, Dft And Implementation
• Integration, Rtl Signoff Tools, Upf/low Power Signoff And Cdc/rdc, Lint
• Strong Domain Knowledge Of Clocking,system Modes. Power Management, Debug, Interconnect, Safety, Security And Other Architectures