Memory Design Engineer

Bangalore | 5+ Years

Key Roles:

• Candidate must have hands-on experience and knowledge of SRAM/ROM compilers or custom memories on various process nodes like 7nm, 14nm, 16nm, 28nm, 45nm, 65nm etc.
• Candidate must have very good understanding of memory architectures, Transistor level circuit design involving critical path modelling, mismatch margin simulations and characterization flows and tools.
• Candidate should have understanding of circuit design concepts for low power CMOS circuits; must have understanding of layout design of memories.