Foundation IP Design & Automation
Compact & high-performing designs are the need of the hour, and InSemi comes as your helping hand in this regard!
We, here at InSemi, work diligently to offer you a comprehensive suite of Foundation IP design services from schematic to layout, including Cadence & Synopsys, and Signoff EDA flow.
InSemi completely understands the concerns around different sizes/types of memories, standard cell libraries, and analog blocks for design and characterization. Thus, after carefully running multiple tests, we offer the best and most sustainable turnkey solutions. For the layouts, the technical design team works with great intensity on custom macros like L1/L2/L3 Cache, ROM, CLK macros; and also possesses exceptional expertise in physical and electrical analysis after the layout. The CAD team also has multidisciplinary expertise across various EDA flows, and automation codes are efficiently scripted in Python, Perl, TCL, and others.
Our Service Offerings
IP Design & CAD
- Circuit Design & Char
- High Speed & Power Management Analog IPs
- PLL/LVDS/LDO/Bandgap Design
- I/O Libraries Design & Characterization
- Std Cell Characterization
- Automation Flow Development using EDA tools,
- Python/Perl/Tcl Scripting
Layout Design
- Process and Layout Migration
- Custom Memory and Memory Compiler
- Analog Layout Design
- I/O Libraries, RF, Serdes Layout
- Std Cell Library Development
- Process and Layout Migration
- Physical Verification for DRC/LVS/PERC
IP Design & Layout Flow
As per the specifications, firstly an ad-hoc design is deliberated. And then after a pre-simulation check, related schematic tests are conducted before the final physical verifications and electrical signoffs.
