by Blog Admin | Apr 23, 2024 | Front End Design & Verification
Key Roles Experienced in rtl design using verilog / system Verilog Asic designers with experiences in all aspects of rtl design flow from specification/microarchitecture definition to design and verification, timing analysis, dft and implementation Integration, rtl...
by Blog Admin | Feb 13, 2024 | Design for Test, VLSI
Key Responsibilities: Experience in dft scan insertion, atpg at ip and soc level Hands on experience in atpg timing and no-timing simulations Proficient in doing basic unit-level verification using simulations. Scan/atpg patterns & test flows development,...
by Blog Admin | Feb 13, 2024 | VLSI
Key Responsibilities: Experience in Static Timing Analysis (STA) for ASIC designs Experience in developing timing constraints Experience in timing closure and optimization Proficiency in using scripting languages such as Perl and TCL Familiarity with EDA tools...
by Blog Admin | Feb 13, 2024 | Front End Design & Verification, VLSI
Key Responsibilities: Expertise in SOC/IP verification Expertise in System Verilog Coding Experience in OVM/UVM/methodology Working environment in APB/AHB/AXI/PCIe/DDR protocol Experience in Test Bench Development Understanding in Gate Level...
by Blog Admin | Aug 17, 2023 | Physical Design, Physical Design and Signoff
Key Responsibilities Technologies Below 14nm……10nm,7nm,latest one ..3nm Block level floor planning and IR drop analysis Block level timing closure with sign off STA Proficient in physical Design methodology which include logic synthesis, placement ,clock...
