Memory Design Engineer

Bangalore/Noida | 8+ Years

Key Responsibilities:

1.Architect and design complex memory circuits—bitcells, sense amps, decoders, write drivers, control logic, compiler tiling—and optimize for PPA, timing, yield, and power.

2.Drive full transistor-level design: perform PVT corner analysis, Monte Carlo variability, leakage control, and robustness margining.

3.Work cross-functionally with memory compiler teams: define tiling strategy, netlist generation, and flow architecture.

4.Partner with layout and extraction teams to identify layout-induced parasitics, IR/EM risk, and propose circuit modifications for robustness.

5.Lead silicon bring-up and characterization: correlate sim-to-silicon, debug issues, and drive flow improvements.

6.Develop and enhance design/validation automation flows using Python, Tcl, Perl, or Shell.

7.Mentor junior engineers, conduct design reviews, influence methodology, and shape memory design strategy.

Qualifications:

1.Bachelor’s, Master’s, or PhD in Electrical, Electronics, Microelectronics, or VLSI Engineering.

2.8+ years of memory circuit design experience at advanced nodes (≥16 nm, FinFET).

3.Demonstrated expertise in SRAM/NVM / register-file design at transistor level.

4.Proficient in EDA tools: HSPICE/Spectre/Custom Designer, plus extraction and reliability tools (Star-RC, QFS).

5.Strong knowledge of process variability, IR/EM trade-offs, layout effects, and power-robustness design.

6.Familiarity with memory compilers, tiling scripts, and netlist/code generation.

7.Hands-on scripting skills in Python, Tcl, Perl, or shell for automation.

8.Excellent communication, cross-functional collaboration, and technical leadership abilities.