by Akshay U K | May 29, 2025 | Uncategorized
Key Responsibilities Responsible for Memory Compiler layout development and verification. Responsible for Layout design and development of Memory blocks such as Array, Row/ Column decoder, sense amplifier, pre-charge, Control blocks for SRAM. Perform layout...
by Blog Admin | Apr 23, 2024 | Front End Design & Verification
Key Roles Experienced in rtl design using verilog / system Verilog Asic designers with experiences in all aspects of rtl design flow from specification/microarchitecture definition to design and verification, timing analysis, dft and implementation Integration, rtl...
