Senior Design Verification

Bangalore | 8+ years

Job description:

• Coverage driven verification using UVM
• Strong System Verilog knowledge along with Assertion coding
• Strong debugging skills
• GLS, XProp and PA sims
• Excellent problem-solving and analytical skills
• Experience with verification methodologies and tools
• Knowledge of scripting languages such as Perl or Python
• Good communication and collaboration skills
• Working experience on protocol like , AXI/PCIe/CXL/Ethernet/DMAC/USB/UFS
• Good leadership skills.