An Integrated Circuit consists of miniaturized components developed into an electrical network on a semiconductor substrate by the photolithography technique. IC Design encapsulates special logic & circuit design techniques for fabricating the IC, and a complex process of various steps is deployed in it. The design flow of the IC starts with system specification and architectural design proceeding to functional and logic design. After that, the circuit is designed and first tested for its correctness through the Physical Design process. Then after the verifications and signoffs, the layout processing is done leading to the final fabrication.
In these steps, the Physical Design process holds great significance as it tests the correctness of logic circuiting. If it is done efficiently then there will be lesser faults and spinoffs. It saves time and cost which can be utilized for more productive tasks. In the long term, the TTM is reduced, and the commercial competitiveness of the organization enhances greatly.
In this article, Team InSemiTech delineates the subtle fineness of the process and throws light on all the aspects. So, let’s delve into the details.
Table of Contents
- Physical Design
- Design Netlist
- Steps in Physical Design Process
2. Physical Design
2.1 What is Physical Design?
In simpler terms, Physical Design is a process of transforming a design idea into a constructible geometry.
In this process, the circuit description is turned into a physical layout- with the position of cells and routes for the interconnection among them.
This is a generalized layout or a schematic representation of an IC. After the deliberations over the layout, the major concern of Physical Design is to work on finding a layout that covers the least possible area and the minimum wire length.
These days, IC designing is split up into two major parts: Front-end Designs- with the Hardware Description Languages, and Back-end Designs with mask layouts and parasitic extractions. Inputs to the physical design come from the netlist, library information on the basic device, and technical information regarding construction constraints.
2.2 Divisions of Physical Design Process
Generally, Physical Design is divided into two main categories:
- Full-Custom Design– In this division, there are no predefined cells. The designer possesses complete flexibility in the layout of the design. In this design, ASIC can be used for the flexibility in modifying design blocks in ASIC libraries.
- Semi-Custom Design: Though the standard cell libraries are developed from a full custom design process but in this division, the different standard library components are used to make the design complete. For example, the components like Half-adder (which are developed from Full Custom Design) are used in unison to make the full adder.
In this division, the designer has flexibility in the placement of cells and routing, but the pre-designed cells are used that are tested with the DFM. For semi-custom design, FPGA is used.
3. Design Netlist
After the synthesis, the first step in ASIC Physical Design Process Flow is getting the design Netlist.
The Netlist is a document of information, generally in textual printed format, detailing the electrical connections among different components on the circuit board.
Generated from the production data, the special Netlist is used to execute the electrical tests, which highlights incorrect or missing connections.
In the synthesis process, constraints are used to ensure whether the design is meeting the functionality and specifications. When the Netlist is verified for timing and functions, the information is sent for the main physical design.
4. Steps in Physical Design Process
After the development and verification of the Design Netlist, there comes the main Physical Design Process. It is mainly a seven-step process, which starts with Floor planning.
4.1 Floor Planning
Sometimes the goals of performance and the space availability conflict with each other and this brings up the need of making components close to each other. For solving such conflicting issues Floor planning phase is pondered first.
It is the phase of identifying structures that need to be grouped and placed together. Based on the design area and the hierarchy, the most optimized floorplan is worked on first. The major parameters to be deliberated include- Macros in design, Memories, placement needs of IP cores, routing possibilities, and the design area.
All of this helps in determining the best IO structure, and the aspect ratio of IC design. If the floor planning is done inefficiently then it will lead to routing congestion and wastage of area.
Data paths are the areas of the design where multiple bits are processed simultaneously with each one being modified in the same way with some of the influence from the bits nearby. Efficient floor planning benefits data paths the most.
There are three inputs for floor planning-
- Set of Modules
- Pins for Interconnections- List of terminals
- The Netlist
There are different approaches to the floor planning process technique. The major one is the Brand & Bound Approach- related to the sizing problems. It includes finding and optimizing the combination of all layouts after the placement. But this approach consumes a lot of time and sometimes gets too delaying for the real instances.
To counter the anomalies, Cohoon developed and implemented a generalized algorithm for the entire floor planning issues. This algorithm makes use of the estimates for the required routing space and ensures the completion of interconnections.
Another heuristic solution for module placement is Simulated Annealing.
After the design area consideration, comes the task of dividing the IC into different functional blocks. The sole aim of this process is to separate the functional blocks from other units, which in turn puts the placement and routing at ease. Such a portioning can also be done in the RTL design phase and then can proceed to design each module separately. These modules are then linked together in the main module- known as the top-level module.
With such a partitioning the circuit gets split and the number of connections between the partitions is minimized.
Subsequent to partitioning, the placement process aims at finding the most suitable physical location for each cell in the block. This not only places the available standard cell in the synthesized Netlist but also helps in optimizing the design.
The main areas targeted within the placement phase are:
- Timing, power, and area optimization
- Routable Designs
- Reducing Congestion
- Minimum Timing DRCs
Inputs for the placement operation include Floorplan definition, Netlist, physical & logical library, technology files, and design constraints.
With all these sets of information, placement is done in two stages:
(a). Coarse placement
During the coarse placement, a dedicated tool approximates the location of each cell with the consideration of congestions, timings, and multi-voltage constraints. Coarse placement is a fast process and is sufficiently accurate for early timing and congestion analysis.
In coarse placement, some of the placed cells might not fall on the right grid and may overlap with one another. Legalization comes into play and using special tools, cells are moved to their deliberated location (called legal location) and all the overlaps are eliminated. Such small location changes might also change the length of wire connections, which in turn also cause new timing violations.
Such violations are then fixed by incremental optimization like resizing the driving cells.
4.4 Clock Tree Synthesis
This phase in Physical Design is operated to eliminate or minimize the skew and insertion delays. This is synthesis, a technique of distributing the clock equally among all sequential parts of the design.
As an input, Clock Tree Synthesis uses placement data and the clock tree limitations. In this phase, buffers are inserted along the clock route of ASIC Design, and this way the clock delays are balanced to all clock inputs.
A clock tree can have various structures. The major one includes-
- Multi-level Tree
Once the synthesis is complete, the timings are cross-checked for the best results.
Inputs on which the Clock Tree Synthesis is done are
- Placement Database
- Inverters / Buffers
- Latency Targets
- DRC Clock Tree
Routing- the interconnections in the PCBs or ICs, in the physical design phase are conducted in two types: global routing and detailed routing.
In global routing, the resources related to connections are allocated first and then the track assignment for the particular net is taken care of.
But the actual connections are made in the detailed routing step while considering all the major constraints like DRC, wire length, timings, etc.
4.6 Physical Verification
As the name suggests, in this step the correctness of the overall layout is conducted. It verifies the:
- Compliance: Whether the design complies with the technical constraints like DRC or not!
- Consistencies: Is the design consistent with the related Netlist
- Antenna Effect: Antenna rule checking is also done.
- Density Verification: At the full chip level
- Electrical Requirements: To check the compliance with electrical requirements
4.7 Mask Data Preparation
This step is also known by the name Layout Post Processing in many places. In this step, the physical layouts are transformed into a set of instructions, which can be used by the photomask writer to create a physical mask. In this phase there are three main steps as follows:
- Chip Fishing: In this step, chip labels and final structures like seal rings, and filler structures are inserted.
- Layout generation: A reticle layout is generated with test patterns and alignment marks.
- Layout to Mask Preparation: This extends the layout data with graphics operations.
After this comprehensive process of Physical Design, the final output is generally attained in GDSII format. This is a data format representing the layout information. After getting data in this typical format the design is sent for verifications and signoffs. Then the layout processing is made which leads to the final fabrication of the IC.