The frenzied outgrowth in electronics, especially in the last two decades, owes to the specifically unremitting growth in semiconductor technology. End users’ frantic & a fervent fetish for meliorated features with no compromise on performance has demanded enhanced technical capabilities.

But an important fact to consider is the design productivity gap as the design teams are not able to fully utilize all the available silicon area to the constraints in design tools & the schedule. The best solution to addressing this design productivity gap is re-using key functions in complex SoC designs. These days, using predefined functional blocks- Intellectual Property is a fate-deciding factor in the design. These IPs are integrated with the new circuitry and other functional components to create a new SoC.

Well, the larger the design team more is the potentiality of errors and inefficiencies due to communication, workflow, and process control factors. This calls for the need for efficient workflow along with more productive resources such as external verification IPs in the design.

This article throws light on the Verification IPs and their efficient development strategy; so let’s delve into the details!

Verification IPs

A well-known strategy in IC design is Semiconductor IP- the pre-developed functionality reducing risk on a design project. A soft IP is shipped in a HDL format, which can be synthesized into several processes and integrated within the design while a hard IP is process specific and the deliverable includes the placement guide of IP within the design. But the main concern in both IPs is the functional capability to the core.

Test benches based on the hardware descriptive language have been the verification norm for SIP for a long, and this was for the design team’s familiarity with HDL and the related capabilities. With the simplicity of IC designs earlier, the performance and debugability were not an issue with this approach.

In a hypothetical design scenario of around 1,000 man-hours, almost 15 weeks would be earmarked for the verification works. In HDL-based verification half of the time is spent on developing the test infrastructures.

This implies that while scaling such a project to larger designs, the successful design management and verification gets exorbitantly expensive!

Also, several studies cite that more than sixty per cent of errors in design are accounted for logic errors, and this fact coupled with the aforementioned example is a clarion call for an effective verification approach. With the consideration of performance and reusability of the compliant verification solutions, special verification efforts are critical for success as this is the sphere where significant savings can be made.

The advanced verification techniques include transaction-level modeling and support, testbench techniques, and integrated assertion support; with these, the user achieves the goals of performance and compliance.

The transaction level modeling raises the level of design abstraction and hence allows the design professional to accelerate the verification process. With this, the simulator needs to go through lesser data so other immediate benefits are improved performance and faster debugging. Tests can be scripted and traced at the packet level – which is much easier to work on.

Another powerful verification tool is assertions, which in their simplest terms enable designers to pass the intent forward. Apart from checking the correctness of behavior, they are used to drive other tools for different analysis tasks as well.

Such advanced verification techniques empower the users to enhance the quality and level of verifications. New languages for test benches like SystemC support more complex verifications like random testing methods and many others. Dedicated coverage tools help define the extent of the test along with the comments on its quality.

Availability of test models drives the successful usage of all such features in test methods. Semiconductor IP development can efficiently leverage these methodologies, and the Verification IP should be developed to fully exercise the implementation of the protocol by IP standards. VIP blocks scan also the simple SIP signals on the model with the equivalent signals of external transactions, facilitating more and better tests.

The strategy of VIP Development

Developing complex SIP demands advanced verification supporting environment. The success of SoC product development relies greatly on the correct functioning of SIP, so it is imperative to motivate the development teams to integrate SIP cores. And this initiates with assessing the IP’s maturity (reliability). The IPs can be selected and assessed from metrics from industry-defined quality- like QIP from Virtual Sockets Interface Alliance (VSIA). The IC design firms must invest considerably in properly selecting & auditing the IP while leveraging the advantage of VSIA QIP or other similar resources.

There are varied tactics for developing VIPs- both from the viewpoint of scripting languages and development methodologies. SystemC and Property Specification Language are used mainly to develop the VIPs.

During the development phase, professionals need to consider wide-ranging alternatives and make the most optimized choices. First is finalizing the developing language, which ideally allows reusable verification blocks for the developer and the SoC integrator as well.

Traffic generation and Monitors are generally the two main kinds of VIPs provided. In many cases, a special compliance test suite is facilitated. This helps assess whether the VIP is offered through the IP standard body or is sponsored.

The monitor helps one ensure the correctness of IP behavior and check that no void transaction occurs.

Winding Up

Verification plays an important role in the success of an SoC development project. If it is developed better than the threshold quality then it not only validates the SIP quality but also verifies the final SoC design with the utmost preciseness.

Enhanced verification methodologies for better coverage, compliance, and interoperability of SIP will pave the way to more and more third-party SIP adoption for a better IC design. The designers have started to access Verification IPs to meet their requirements in challenging deadlines.

Proper VIPs also empower the SIP developers to mitigate and manage the associated risks with core development and increase its adoption in the development of complex SoCs.