Prologue

The tactics and tools a design team selects are of pivotal importance in any project’s success. Being competitive in today’s semiconductor industry is about adopting all-inclusive, flexible, and scalable solutions. Then only one can cut implementation times, testing costs, and an overall TTM.

An important phase in the whole design process is the DFT (Design-for-Test) which encompasses a vast range of design-related test tasks. Finding its application right from the validation of test logic during RTL designs and investigation of failure analysis of the field returns, the DFT application continues all way to performance monitoring, fault chances, and security concerns.

This article delineates the details of advanced DFT solutions by InSemi and delves into the dividends it renders to the semiconductor businesses.

Detecting Defects- Faster & Better

The fundamental function of DFT practice is to spot the flaw in developed silicon and to make sure that in the final system it functions as ideated.

All possible defects a DFT system can detect is known as Defect Coverage.

For this, William, in 1981, developed a formula for predicting defect level in terms of yield:

Defect Level = 1 – Yield (1- Defect Coverage)

The level of defect is generally expressed in terms of DPPM (defective parts per million). If there are too many defects that an organization failed to detect and shipped the product, then one is going to suffer, greatly!

The defects can be in any form viz. transition delays, stuck-at, IDDQ, cell-aware, bridging, path delay, and many more.

Though William’s formula seemingly makes it simple to get DPPM rates but applying this equation is somewhat not so easy as precise knowledge of variables is hard.

InSemi has made exceptional advances in defect-based tests, which are more like the fault models on physical designs, oriented at area identification where fault can occur.

This includes a complete suite of fault models and test patterns generation platforms that target defects in SoCs or ICs at the transistor’s interconnection level- assisting clients in detecting flaws that would go unnoticed with a conventional approach.

Another special approach includes Memory Built-in Self-Test. This is for detecting failures in embedded memories and interface logic. The more and more on-chip storage capabilities, which are now exceeding Gigabits of embedded SRAM- the new industry norm, are a challenge for Memory BIST.

Here, the hierarchical DFT methodology, which requires complete automated solutions with user directives across all parameters, comes to the rescue by InSemi. Furthermore, access time to all BIST controllers and access to fail data for volume analysis of memory test failures is also vital component.

InSemiTech works in close collaboration with IC/SoC designers and ‘memory’ providers to continuously confirm our BIST solutions over the state-of-the-art techniques and memory designs.

Improving Yield with DFT

With advances in IC technologies, leading to variations in geometrical and process fronts, manufacturers are witnessing a drop in yield with greater ramp-up time. A reduction in the number of failing dies and better reliability of the production process has a direct & overt impact on business.

For addressing these issues DFT methodology comes to the rescue by detecting defects at initial levels and reducing manufacturing complexities during high-volume productions.

Structural test patterns are used to detect the failing die before being shipped to the client’s destination. The data garnered through these investigations offer treasured data regarding the failure causes, which can be used to increase the yield and lessen TAT.

The all-inclusive analysis of fail-test data, known as Scan Diagnosis, develops a set of defect suspects and précising the defect location.

Diagnosing & fixing a yield-related problem means a thorough understanding of the defect/failure mechanism not only over an individual die but also across all related components. The number of failing dies can span across several wafers or even various lots. Therefore, insights gained from the scan diagnosis offer a competitive advantage, leading to greater profitability.

Fabless clients who have the design can also generate an ample volume of diagnosis results and analyze them to correlate with PFA findings. This helps track defect causes and reduces the excursion cycles. Such an approach with the DFT methodology greatly lessens the turnaround time and improves yield efficiency considerably.

Streamlining the Test Flows

Any single tool related to DFT, or the methodology is not substantial in leveraging the full test potential. The toolset works best when developed on a shared database, leading to a unified platform, serving as an intent-driven environment.

InSemiTech couples up everything together in a tidy hierarchical DFT environment, and help detect defects, improves yield, and accelerate your product to the market.

Some special technical fields keep on pushing the limits of conventional tools & tactics. For example, Artificial Intelligence processors are typically very large and complex. They even consist of thousands of duplicate processor arrays; all requiring a high-test coverage. Without a hierarchical DFT methodology, there is no solution to manage this volume, as it divides the task into smaller bits. The coverage requirement needs many fault models, making embedded compressions highly aggressive!

Reliable technologies are not developed or provided by design automation vendors but require constant and collaborative work among the industry partners.

And here the domain expertise of industry leader InSemiTech comes into play.

Winding Up

The complexities are soaring high, and the semiconductor developers have to refine and optimize all the aspects of design & fabrication. Today’s highly competitive electronics industry demands every component of your product to contribute to the success, not increasing the barriers. Those simple scan compressions and conventional test patterns are no longer a successful recipe.

The complete suite of DFT methodologies, implemented by InSemiTech, is developed in close collaboration with domain leaders to provide scalable & trustworthy technologies. Our DFT technology services are designed to integrate all test functions in one place, with one database and a universal infrastructure.

Whether your goal is to meet ISO 26262 safety standards, reduce design excursions and costs, meet the deadline, or enhance the yield, team InSemiTech is there for your help with the overarching range of state-of-the-art DFT technology solutions.

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