Since the dawn of the electronics industry and throughout the history of electronic circuits Moore’s Law had hold true every time!
To meet the ever-enhancing expectations in terms of features & functionality, the design teams are working very hard to create more and more advanced process nodes. Transistor counts on an advanced processor now go in the range of tens of billions!
A key technology trend that has been a driving force in the semiconductor industry and transmuted today’s advanced processors is the FinFET Process.
It is a special transistor design which overcomes the worst of the short-channel effect in the transistors and empowers the chips to gain higher performance metrics at much lower costs.
In this article, Team InSemi throws light on various aspects, cutting edges, market trends, and the usage of FinFET technology. So let’s delve into the details.
What is FinFET
FinFET stands for Fin Shaped Field Effect Transistor.
It drives the name from its design as it has a fin-shaped body. The silicon layer that forms the main body of the transistor is fin-shaped and this distinguishes it from traditional transistors. Professor Chenming Hu, Tsu-Jae King-Liu and Jeffrey Bokor at the University of California, Berkeley were the ones who coined the term.
And as the electric field controls material conductivity, it’s a field effect transistor.
Also, in contrast with the conventional 2D planar transistors, FinFET is a three-dimensional one with an elevated channel on which the gate wraps around.
FinFETs generate a lower leakage power and facilitate a greater device density- all thanks to their special structure! They operate at lower voltages while offering higher drive current. These features in unison imply a higher performance is packed into a relatively smaller area while greatly lessening the cost of performance.
Background
FinFET technology is the result of relentless advancement in integrations. To achieve ultra-large integrations, many parameters of the transistors needed a change. Especially the size was required to be reduced so that many more units could be packed within a given area. Other parameters are power dissipation, line voltage, and increased performance frequency.
As the process technologies are shrinking and 20nm dimension is a norm so the scalability of the individual device is constrained. Moreover, optimizing one parameter (say performance) results in compromising the other areas (say power or area).
Another issue in this regard is that as small feature sizes are used in chip technologies the source and sink of the used MOS devices are used to breach into the channel. This is used to make the leakage current flow among them. This never made the transistor off totally!
Therefore the need was to have a change in the traditional transistor structure to optimize the overall system.
The first 25nm FinFET transistor operating at 0.7V was demonstrated by TSMC in Dec 2002. But the first commercial 22nm FinFET became available a decade later. The gradual improvements have made greater strides in the direction of improving PPA goals.
FinFets in Place of Planar Transistors
The need for more & more computational powers means enhanced computational density. For this, more transistors would be required and this will increase the chip area. But practically, the developers not only need to keep the area the same but most of the time are constrained to reduce the sizes as well.
One solution can be to decrease the transistors’ size. But first of all, this is not practical always as 7nm nodes are also there so lessening the transistor size is limited. Secondly, if the dimensions are decreased, the distance between the source & drain will also decrease. With this, the gate electrode’s ability to control current flow in the channel region will also suffer detrimentally.
For this, the planar transistors (MOSFETs) can suffer short-channel effects.
Another solution has been pointed out in literature by changing the material of the chip but this aspect might not be possible for the financial factors.
But on the other hand, FinFETs exhibit superior short-channel behaviour. They also have a lower switching time and a higher current density than conventional planar ones.
Calculating FinFET Transistor’s Width
The fin (channel) of the transistor is vertical and this device requires the consideration of specific dimensions. FinFET exhibits the‘ width quantization’ property- which means random widths are not possible; it must be in the multiple of its height.
As fin thickness controls the short-channel behaviour (the main advantage), so it holds a pivotal importance.
Another aspect is subthreshold swing- a measure of the transistor’s efficiency, which is a variation in gate voltage that increases the drain current in the order of magnitude.
Fig. FinFET dimensions- Based on King Liu, 2012
As per this figure,
Lg is the Gate Length
T is the fin thickness
Hfin is the Fin Height
W is the transistor width
Weff is the effective transistor width (for the multiple fins)
For double-gate: W = 2 ∙ Hfin
For tri-gate: W = 2 ∙ Hfin + T
Multiple fins will increase the transistor width.
Weff = n ∙ W
Where n = number of fins
Competitive Edges & Roadblocks of FinFET Technology
- Size: FinFET allows passage through a 20nm barrier, which was used to be considered as the endpoint.
- Power: the adopters of the technology have reported around 150% improvements. Much lower power consumptions facilitate higher integration levels.
- Operating Speed: In most cases, the reports are about 30% faster execution.
- Operating Voltage: For the lower threshold voltage, FinFETS operate at much lower voltages than others.
- Static Leakage Current: is reduced up to 90%
- Short-Channel Effect: Greatly Reduced
- Channel Control: FinFETS facilitates better channel control.
The discussion revolved mainly around the leading edges but FinFET technology is not perfect in all senses. Some roadblocks are also there like:
- Difficulty in controlling Voltage Threshold
- Higher Parasitic due to the 3D structure
- Higher Capacitance
- Quantized Device Width
- Higher Fabrication Cost
Another aspect to consider is the Corner Effect. The electric field at the corner is always amplified when compared with the field at the sidewalls. But this effect can be lessened by using a nitrate layer in the corners.
For the competitive edges that the FinFET technology renders it has been welcomed by the electronic industry with open arms. A Data Bridge Report published by Globe News Wire on 23rd Sep 2022 revealed FinFET Technology Market is Likely to Grow at a CAGR of 40.85% and is expected to reach a worth of USD 149.01 Billion by 2029.
Beyond FinFET and Below 5 nm
The natural next step to continue scaling transistors, especially below 5 nm, is to continue wrapping the gate around the fourth side of the channel region. This structure is called gate-all-around FET (GAAFET). Some possibilities include growing nanosheets or nanowires from silicon or III-V materials and using the structure as the channel region. Other possibilities include using alternative materials (e.g., graphene) in the standard FinFET structure. No matter what architecture is used, designers will need the right tools to design, model, and integrate their FinFET circuits into larger systems.
