Prologue 

The number of transistors, the logical connections, and the related overall complexity of a chip design are soaring high with each passing day! 10 million random logic points are a common scene for an IC. Such a large-scale integration offers a great user experience arising out of their superior performance, but the problem lies in testing such designs. 

Today the functional units within a single design are as complex as the entire chip used to be some times ago. If any problem occurs in any logic connection of a single unit then the overall functionality of the chip will be adversely affected. The added complications in terms of size, time, and the related complexities in fabricating a chip can be eased up with a proven design & test approach. Here an overarching DFT methodology comes to the rescue.

In this article, InSemiTech put a light on the need for DFT services and explains why it is a critical element for your product’s success.

Why DFT is need of the hour?

A better fault coverage in the design part ensures that minimum possible defected parts escape from the attention. Moreover, shorter test production and lesser iterations in the chip fabrication reduce the time to market- enhancing the business competitiveness by lessening the production cost and taking the final product to market fast. 

So, in a nutshell, DFT ensures a fast debug & diagnostic, improves the product yield, and helps reduce TTM. 

How do DFT techniques work?

In the chip development lifecycle, DFT is used across varied phases viz. Design, Test Generation, First Silicon, Chip Test, Board-Level Test, and System Level Test. 

In the design phase, test structures are inserted- either manually or in an automated environment. This is the phase, wherewith the testability, most of the cost savings can be made. With every subsequent stage, the testing cost greatly increases for the complexities, so the major test focus must be made at this phase. 

The dedicated expertise around DFT tools at InSemiTech quantifies the testability of each design component from the functional units of the chip; traversing all way to the design hierarchies to the full chip. InSemiTech addresses problems at each level and sets & meets the targets stringently.

Next comes the test-generation phase. Here DFT is used to accelerate the ATPG process. Another consideration is the use of additional fault models. The ‘stuck-at’ fault model has been the traditional work pattern for long but many defects are there which cannot be modeled with this old-school technique. Here also DFT comes into play and successful detection of all faults becomes much easier with it. 

The subsequent step- First Silicon is where all the units come together and the benefits of DFT’s hard work are witnessed. In this part, the DFT attention is focused on diagnostics and characterization. Then, at the chip production phase, our DFT services ensure the overall quality of the product to be shipped. The small pattern count with high test coverage acts as a yardstick to adjudicate the functional and non-functional wafers. For the functionally working ones the diced chips are reinvestigated to ensure the final product. 

By enabling a single universal pattern to detect multiple defects, the DFT methodology also facilitates smaller pattern sets for individual faults. This, in turn, reduces ATE time and the related cost. The more is the test coverage for a given set, the better is the quality of fabricated chips. And the lesser the amount of failing chips made into the product, the lesser is the replacement cost. 

Sometimes, after this step, a ‘burn-in’ test is also conducted, where they are stressed in heating devices to simulate the temperature extremes and operational life. If the chip has gone through the right DFT methodologies in the previous phases the burn-in test will produce more meaningful chip failure data. 

What are DFT reports? 

The test review aka Design for Testability occurs prior to production. The reviews are centered on picking up the potential problems at their earliest, and resolving them so that they don’t become a bigger problem later. A good Design for Testability not only includes the strategies preventing manufacturing defects but also deters the defective product from leaving the foundry or physical design facility.

Such DFT reports hold greater significance when the product goes through a significant design change. As per the designs, test criteria, and assembly; the report is continuously updated. These reports enable the re-development and help identify the flaws before they cost actual money in the production line.

Why DFT reports are important?

As discussed, the DFT reports are assembly methodologies aimed at maximizing quality and minimizing production costs. Specifically, DFT reports help to achieve the following dividends:

  • The all-inclusive analysis of the client’s intellection
  • Ensuring a consistent quality across all batches
  • Eliminating the need of extra development steps        
  • Detecting & doctoring errors before production
  • Complete evaluation of PCB Assembly Design
  • Better circuit testability through trace routing
  • Almost Zero Risk Transfer to the end customer 
  • The best possible product yield in lesser time 

In a nutshell

Specialized DFT services yield multi-faceted benefits- faster development, better quality, easy diagnosis, better quality- to name a few. But the need is to ensure state-of-the-art testing procedures and tools. Otherwise, it can add to the circuit timing and more complexities for the design facility. Without DFT, the product quality and TTM are going to be affected adversely.   

To get the best results, DFT requires robust tools and strong support. The tests must be capable of handling myriads of structures in a single design and working with various fault models. And all this with a speedy result generation over multimillion logic connections!

In all the requirements regarding the specialized DFT services, Team InSemiTech is always there to proffer a helping hand and ensure the success of your electronic product. 

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