Gordon Moore, an Intel co-founder observed that from the time of the IC’s invention, the number of transistors per square inch on an IC was doubling approximately every two years. The observation was in the year 1965 and has been recognized as Moore’s law. His observations helped in the creation of better-performing, cost-effective, and small-sized chips. 

In the last couple of years, the focus has shifted towards the creation of smaller transistors, which execute signals faster and are better at power efficiency. This is known as a lower technology node.

Though the technology is transforming the electronics world and is revolutionizing the IoT with smaller devices the problem lies in their testing & validation. For lower technology nodes, there is a need for ultra-sophisticated DFT infrastructure, which can reduce the iterations and generate data for potential faults.

This article delineates how team InSemi helps global clients in testing & validating LTN with its state-of-the-art DFT infrastructure

How InSemi Helps ?

In lower geometry nodes, power consumption and a tremendous volume of data in the testing process have grown exponentially; and are a challenge to the testing teams. Design for testability is the most effective solution that saves high design cost, execution test time, area, and various faults in the testing phase only

So, let’s delve into the details regarding the DFT architecture of InSemi that help overcome various barriers.

1. Reduced Pin Count Testing

The current scenario demands the ICs to be in the 7nm range, and the number of I/O pins on processors is increasing. With the gigantic rise in transistor counts, the costs of higher testing facilities also increase proportionally. To achieve greater quality tests across more logic gates, the test patterns and the process cycle also need to be improved

In this regard, team InSemi adopts a sophisticated test technique- RPCT. Reduced Pin Count Testing is a solution that allows the application of speed test patterns with low-cost testing units that have limited pins. This also helps in the optimization of coverage and implementation test time with no or negligible changes in IC design

With this technique, the DFT technicians get empowered for testing the inputs/outputs logic in limited scan standards. Within the limitations, the maximum fault coverage is achieved, and the usage of cost-effective testers keeps hardware design within budget.

2. Scan Insertions & Compression Techniques

Compression techniques in DFT are mainly aimed at optimizing the tester application timings. On the other hand, the data volume areas are optimized by scan insertions

With these two modus operandi in the DFT methodology, our team can achieve high testing quality for SoCs and ASIC at a very low cost

Low Technology Nodes are also associated with power density and higher heat dissipation, both cause damage to ICs. To counter these challenges, our technicians call for clock gating, and voltage shutoffs in the functional mode with greater observations and control. Observing the change values in the required logic at the output and controlling the signal to logic value in the input – our technicians also take care of the DRC violations

3. Simultaneous Handling of Multiple Fault Categories

Following are the potential faults in the Lower Technology Nodes:

a) Processing Fault: Missed connections, parasitic components, and oxidation layer breakdown are the most common issues in smaller ICs; needing attention from the starting phase

b) Crystal Imperfections: Defects in the IC’s crystals, cracks in the base, and surface impurities are some faults in the components from which IC is being fabricated

c) Voltage Faults: Dielectric failure at higher voltages and electro-migration decay against the repeated voltage supply makes IC lose their actual properties

d) Short-circuit faults: Defects on the PCB like bare wires or loose wires may cause short circuits and need immediate attention. These issues are also known as bridging defects.

e) Defected Packaging: Sometimes during the packaging of ICs the logical connections degrade and sometimes the seal is not perfectly enclosing the IC.

f) Transient Faults: Due to fluctuations in power supply non-repairable physical damages occur in ICs.

g) Recurring fault: Sometimes due to lose connections or partly defective components some faults occur then disappear, and then come again after some time when power is connected to IC

h) Delayed Response Fault: This interprets the output being received after a significant delay.

i) Functional Defects: Inaccurate functioning of the IC system at the logic gate level comes under this category

4. Low Power Design & Management

With the shrinking size of ICs, low-power design has got greater prominence, but this raises concerns for the test team in regard to the pertinent faults. Design for testability and lower power design are closely related to each other. Using the power test access mechanism DFT is applied to increase the power dissipation during Automatic Test Pattern Generation.

Few important low power management tactics include- Connection of functional block with power domain, multiple supply voltages through level shifters, Isolated Logic Cells, Clock Gating, and Retention Cells

5. Test Point Insertions

Test points offer an extra set of input & output units within the internal parts of the circuit. This helps the testing technician to detect the fault coverage, as with this tactic the uncontrollable becomes easily controllable, and the things hard to notice get easily observed on the ‘on-chip’ testing.

Test point insertions and the related efficiency developed in the test flow are the standards for a quality circuit design, within the DFT methodology.

Winding Up

Winding Up As the chip size and the size of the transistors continues to shrink, to meet the increasing demands, global businesses are facing challenges in physical designs and their related testing. The faults increasing the design iterations not only increase the production cost but also lengthen the TTM- depleting the competitiveness!

Apart from the general test issues, Low Node Technology has its own set of different roadblocks. There is a need for specialized professionals, DFT architecture, and successful experience in the domain. And for all these, team InSemi is always there to proffer a helping hand.