Preferred Education

  • BTech/Mtech

Area of Expertise

  • Strong background and direct experience in CMOS transistor-level circuit design
  • Deep understanding of device physics, electrical/reliability behaviors in both advanced bulk and FinFET technologies, scaling limitations, etc. Familiarity with basic semiconductor manufacturing processes
  • Familiarity with variation-aware design in nanometer technology nodes. Understanding of statistical concepts/methodologies
  • Physical implementation (layout) and layout supervision
  • Familiarity with ASIC frontend/backend integration flows, IP delivery collaterals including behavior model, upf lib, LEF view, etc
  • Silicon Tape Out and debug experience, noise-aware design experience is plus
  • Automation (shell/Perl or python) semi-custom or custom design experience with typical PnR tools etc. will be a significant plus
  • Candidate is expected to work with multisite teams and should have excellent communication skill

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