Preferred Education

  • Any Degree is fine

Area of Expertise 

  • Experienced in RTL design using Verilog / System Verilog
  • ASIC designers with experiences in all aspects of RTL design flow from Specification/Microarchitecture definition to design and verification, Timing Analysis, DFT and Implementation
  • Integration, RTL signoff tools, UPF/Low power signoff and CDC/RDC, Lint
  • Strong domain knowledge of Clocking, System modes, Power management, debug, interconnect, safety, security, and other architectures
  • Highly motivated, self-starter with good interpersonal skills and a strong team player
  • Excellent communication, critical thinking, and problem-solving skills

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